Crate rustyn64_cpu 

rustyn64-cpu — NEC VR4300 (MIPS R4300i) main CPU.

64-bit MIPS III core: 32 general-purpose registers, HI/LO, the CP0 system-control coprocessor (TLB + exceptions), the CP1 FPU, and the SysAD bus interface. This is a skeleton — the real interpreter/JIT, the TLB, and the FPU are major roadmap phases. Behavior is pinned against n64-systemtest FIRST (test-ROM-is-spec), then implemented until it passes.

Part of the one-directional chip-crate graph (see docs/architecture.md): this crate does NOT depend on any other chip crate. It talks to the rest of the machine through the Bus trait, which rustyn64-core implements. #![no_std] + alloc so it cross-compiles to a bare-metal target; only the frontend carries std + unsafe.

Re-exports

pub use addr::Cached;

pub use addr::Physical;

pub use addr::Segment;

pub use addr::segment;

pub use addr::translate_via;

pub use alu::HiLo;

pub use alu::MulDiv;

pub use decode::Decoded;

pub use decode::Op;

pub use decode::decode;

pub use exec::Executed;

pub use exec::WriteBack;

pub use exec::execute;

pub use mem::LoadKind;

pub use mem::StoreKind;

pub use pipeline::Exception;

pub use pipeline::Interlock;

pub use pipeline::Latch;

pub use pipeline::Pipeline;

pub use pipeline::Stage;

pub use regs::Regs;

pub use sysad::BlockOrder;

pub use sysad::Phase;

pub use sysad::Transaction;

pub use sysad::Width;

pub use sysad::block_order;

Modules

addr

Virtual → physical address translation (T-11-006, T-12-004).

alu

The VR4300 integer ALU as pure functions (T-11-002).

cache

The VR4300 primary caches (T-11-003).

cop0

COP0 — the VR4300 system control coprocessor (T-12-001).

cop1

COP1 control registers (T-12-006).

decode

MIPS III instruction decode (T-11-002).

exception

Exception dispatch — the epilogue and the vector table (T-12-002).

exec

EX-stage execution: Decoded plus operands in, result out (T-11-002).

fpr

The floating-point register file (T-13-001).

fpu

FPU arithmetic (T-13-002).

mem

Load/store data shaping (T-11-003).

pipeline

The VR4300’s five-stage pipeline (ADR 0007).

regs

The VR4300 register file.

softfloat

Soft-float arithmetic with exact IEEE-754 exception flags (T-13-003).

sysad

The SysAD bus transaction model (T-11-008).

tlb

The joint TLB and the instruction micro-TLB (T-12-004).

Structs

Cpu

NEC VR4300 architectural state.

Enums

BusPhase

Which half of a SysAD bus transaction is on the wire.

Traits

Bus

The system-memory bus the VR4300 borrows during Cpu::tick.

Functions

version

Returns the crate version string.