pub struct Cpu {
pub regs: Regs,
pub pc: u64,
pub pipeline: Pipeline,
pub retired: u64,
}Expand description
NEC VR4300 architectural state.
This is the skeleton register file only; the decode/execute pipeline, the CP0 TLB, and the CP1 FPU are roadmap phases left as marked TODOs.
Fields§
§regs: RegsThe register file: 32 GPRs plus HI/LO. $zero’s hardwiring lives in
Regs::read/Regs::write so no call site can forget it.
pc: u64Program counter (virtual address).
pipeline: PipelineThe five-stage pipeline: four inter-stage latches plus control state
(ADR 0007). Advanced one PClock per Cpu::tick.
retired: u64Retired-work tally: instructions retired since power-on, for the golden-log differ.
This is not a time position and nothing schedules against it — the
scheduler derives every cycle position from its one master_ticks counter
(ADR 0006). A work tally is the one kind of counter that is still allowed
to be incremented; see System::cpu_cycles() for the CPU’s position.
Implementations§
Source§impl Cpu
impl Cpu
Sourcepub const fn new() -> Self
pub const fn new() -> Self
Construct at power-on / cold reset.
gpr[0] is the architectural zero register. Any phase alignment, where
applicable, comes from the seeded scheduler PRNG (the determinism
contract — see docs/adr/0004), never the OS RNG.
Sourcepub const fn set_pc(&mut self, pc: u64)
pub const fn set_pc(&mut self, pc: u64)
Set the program counter (used by golden-log automation harnesses).
Sourcepub fn tick<B: Bus>(&mut self, bus: &mut B)
pub fn tick<B: Bus>(&mut self, bus: &mut B)
Advance the CPU by one PClock — not one instruction.
The scheduler calls this on every CPU edge (every 2nd master tick, ADR
0006). At least 5 PCycles are required to execute an instruction (UM
§4.1), and DDIV stalls the whole pipeline for 69 (UM Table 3-12), so a
tick is emphatically not an instruction.
Hot path: keep allocation-free (no Vec/Box in tick). The bus
argument is the &mut Bus the scheduler hands down each step.
Prefer Cpu::tick_at when a scheduler is present. This path holds
the COP0 Count timeline still, because Count is derived from the
master clock (ADR 0006) and this function has no access to it — so
Count/Compare and the timer interrupt do not advance. That is
deliberate: guessing a rate here would be wrong, and Count runs at half
PClock, not one step per call.
Sourcepub fn tick_at<B: Bus>(&mut self, bus: &mut B, count_now: u64)
pub fn tick_at<B: Bus>(&mut self, bus: &mut B, count_now: u64)
Step one PCycle with the scheduler’s Count timeline supplied.
The scheduler owns master_ticks and derives count_ticks from it
(ADR 0006); the CPU turns that into the architectural, guest-writable
Count. Passing it in rather than incrementing locally is what keeps
master_ticks the only incremented counter in the core.