Expand description
The SysAD bus transaction model (T-11-008).
The CPU reaches everything outside its caches through SysAD, a packet
protocol — not a simple addressed read. A transaction is an address cycle
carrying a command, then a data cycle carrying the payload, handshaked by
EOK / Pvalid / Evalid, with an unbounded wait between them. That wait
is where real RDRAM latency lives.
§Why model it at all
Neither reference emulator does. CEN64 completes the whole access atomically
in zero emulated time and charges a flat constant (its own source says
// Currently using fixed values....); ares charges different constants. They
disagree on the value and neither derived it from a spec. Modeling the split
is where this project can be better rather than equal — and it is what makes
the bus access a point the scheduler can interleave the RCP around, which is
the whole reason ADR 0007 models a pipeline.
§Clock domain
SysAD runs at SClock = MClock = 62.5 MHz, so one bus cycle is 1.5
PCycles — 3 master ticks against the CPU’s 2 (ADR 0006). A transaction is
therefore not a whole number of CPU cycles, which is exactly the
“1 to 2 PCycles: synchronize with SClock” indeterminacy the manual
charges in Table 11-1.
Structs§
- Transaction
- A bus transaction in progress.
Enums§
- Block
Order - The order a block transfer’s 64-bit halves arrive in.
- Phase
- Which half of a transaction is on the wire.
- Width
- Transfer size, encoded in
SysCmd(1:0)of a request.
Functions§
- block_
order - The ordering a read of
widthataddruses.