Module mem 

Load/store data shaping (T-11-003).

Pure byte-level transforms: no bus, no registers, no addresses beyond the low bits that select alignment. The pipeline’s DC stage performs the actual access and calls these to shape the result.

The unaligned family is the interesting part

MIPS has no unaligned load instruction. Instead LWL/LWR (and LDL/LDR for doublewords) are used as a pair to assemble an unaligned value from two aligned accesses, each merging part of the addressed word into the destination register while preserving the rest of it.

The N64 is big-endian, which decides the direction of every shift here. LWL takes the bytes from the addressed byte to the end of the containing word and places them at the top of the register; LWR takes the bytes from the start of the word up to the addressed byte and places them at the bottom. Getting the endianness backwards produces plausible-looking values that are wrong only for unaligned addresses, which is a miserable bug to find.

Enums

LoadKind

Width and signedness of an aligned load.

StoreKind

Width of an aligned store.

Functions

ldl

LDL — the doubleword form of lwl. byte is addr & 7.

ldr

LDR — the doubleword form of lwr.

lwl

LWL — merge the bytes from the addressed byte to the end of the containing word into the top of rt, preserving rt’s low bytes.

lwr

LWR — merge the bytes from the start of the containing word up to the addressed byte into the bottom of rt, preserving rt’s high bytes.

sdl

SDL — the doubleword form of swl.

sdr

SDR — the doubleword form of swr.

swl

SWL — merge the top bytes of rt into the addressed word.

swr

SWR — merge the bottom bytes of rt into the addressed word.