pub enum BusPhase {
Command,
Data,
}Expand description
Which half of a SysAD bus transaction is on the wire.
The VR4300 talks to the RCP over the SysAD bus, which multiplexes the command
and the data onto the same lines; SYSCMD bit 4 is documented as “Command or
Data” and this enum mirrors that split.
This describes the bus protocol and carries no interrupt semantics. An
earlier revision paired it with a poll_irq_at_phase(BusPhase) hook, on the
assumption that interrupts are sampled at a particular half of a transaction.
No such coupling is documented anywhere — not in the User’s Manual, not on the
wiki. The documented rule (UM §4.7.1) is per-PCycle and gated on stall state:
“NMI and interrupt exception requests are accepted only if the previous
PCycle was a run cycle.” That hook was shaped on the wrong axis and was
removed rather than completed (ADR 0007).
SysAD runs at SClock = MClock = 62.5 MHz, so one bus cycle is 1.5 PCycles — 3
master ticks against the CPU’s 2 (ADR 0006). This is not the deferred ADR
0005 refactor, which concerns resolution finer than one PClock.
TODO(T-11-008): the transaction model that actually uses this.
Variants§
Command
The command half — the CPU drives SYSCMD and the address.
Data
The data half — the transfer itself, and where the result commits.