Module tlb 

The joint TLB and the instruction micro-TLB (T-12-004).

32 fully-associative joint-TLB (JTLB) entries, each mapping an even/odd page pair, plus a two-entry instruction micro-TLB (ITLB) in front of it.

The distinction that is easy to lose

A micro-TLB miss is a stall (3 PCycles, UM §4.6.2 p. 107); a JTLB miss is an exception. An implementation with only the JTLB does not approximate the micro-TLB’s cost — it deletes the structure the cost occurs in, so there is nowhere left to charge it.

The matching rule, and the trap in it

An entry matches when VPN2 matches and (G is set or the ASID matches). The V bit does not participate (UM §5.4.9, p. 155):

“While the V bit of the entry must be set for a valid translation to take place, it is not involved in the determination of a matching TLB entry.”

So an invalid entry still matches — it just raises TLB Invalid instead of translating. Checking V during matching looks like an optimization, passes ordinary tests, and breaks two things: an invalid entry would fall through to a refill (wrong vector, wrong handler), and TLB shutdown would stop firing on duplicates involving an invalid entry, which UM Fig. 6-6 (p. 167) explicitly says it must.

Structs

Entry

One JTLB entry: a VPN2 tag plus the even and odd page it maps.

PageEntry

One half of an entry — the even or odd page.

Tlb

The joint TLB plus its instruction micro-TLB.

Translated

A successful translation.

Enums

TlbFault

Why a translation failed.

Constants

ASID_MASK

The EntryHi.ASID field mask.

ITLB_ENTRIES

Instruction micro-TLB entries (UM §1.5.1).

ITLB_MISS_PCYCLES

The micro-TLB reload penalty, in PCycles (UM §4.6.2, p. 107).

JTLB_ENTRIES

JTLB entries. Fully associative (UM §5.1, p. 122).

VA_MASK

The bits of a virtual address that EntryHi.VPN2 can hold: VA(39:0).

VPN2_MASK

The EntryHi.VPN2 field mask.