Module exception 

Exception dispatch — the epilogue and the vector table (T-12-002).

Short, and every line of it is load-bearing. The hardware sequence is UM Fig. 6-14 (p. 201) for the general case and Fig. 6-15 (p. 203) for TLB refills.

The EXL gate is the whole point

EPC and Cause.BD are written only when EXL was already 0. The flowchart’s EXL = 1? test precedes the EPC write, commented “Check for multiple exception”, and UM §6.3.7 (p. 174) states the reason directly:

“The EXL bit … is set to 1 to keep the processor from overwriting the address of the exception-causing instruction contained in the EPC register in the event of another exception.”

An implementation that always writes EPC passes every single-exception test and corrupts every nested one — and nesting is not exotic: UM §6.4.8 (p. 188) describes a TLB refill handler taking a second TLB miss as the normal path.

The 0x080 trap

UM Fig. 6-15 (p. 203) routes a refill with EXL = 1 to offset 0x080. That figure is wrong, and the manual contradicts it three times — see vector and accuracy-ledger S-3.

Modules

exc_code

Cause.ExcCode values (UM Table 6-2, p. 172).

Structs

Dispatch

The result of dispatching an exception.

Enums

VectorKind

Which vector an exception uses.

Constants

EPILOGUE_STALL

The documented stall on taking an exception (UM §4.7, p. 114).

Functions

dispatch

Perform the exception epilogue and return where to vector.

eret

ERET — return from an exception (UM Ch. 16, p. 434).

exc_code_of

The ExcCode an exception reports.

nmi

Perform the exception epilogue and return where to vector.

vector

The exception vector address (UM Tables 6-3/6-4, p. 181).

vector_kind_of

Which vector kind an exception takes.

writes_bad_vaddr

Does this exception write BadVAddr?