pub enum Width {
Single32,
Single64,
Block128,
Block256,
}Expand description
Transfer size, encoded in SysCmd(1:0) of a request.
Variants§
Single32
32-bit single transfer. All 8/16/24/32-bit reads are issued as this; the CPU does the shifting internally.
Single64
64-bit.
Block128
128-bit block — a D-cache line.
Block256
256-bit block — an I-cache line.
Implementations§
Source§impl Width
impl Width
Sourcepub const fn beats(self) -> u32
pub const fn beats(self) -> u32
32-bit beats on the bus, which is what the data phase costs.
The VR4300’s SysAD is 32 bits wide, not 64. This is the headline
cost reduction against the R4400 and it is easy to get wrong, because
the CPU is a 64-bit machine internally and most MIPS III documentation
describes a 64-bit external bus. The manual is explicit (§1.3): “It
contains a 32-bit multiplexed address/data bus, with per-byte parity …
It is not compatible with the System interface bus used on the VR4400”,
and every signal reference in it is SysAD(31:0).
So a 128-bit D-cache line is 4 beats and a 256-bit I-cache line is
8, not 2 and 4. Halving these would make every cache fill finish twice
as fast as hardware.