Module alu 

The VR4300 integer ALU as pure functions (T-11-002).

Kept free of pipeline and register-file state on purpose: every rule here is a property of the arithmetic, so it can be tested exhaustively without constructing a machine. The pipeline calls these from EX.

The two rules that dominate MIPS III

32-bit results are sign-extended into the 64-bit register. Every *W-class operation produces a 32-bit value that is then sign-extended to 64 bits before it reaches the register file. Skipping this is the single most common source of MIPS III emulator bugs, because it is invisible until a program compares or branches on the upper half.

The documented errata are reproduced, not corrected. SRA/SRAV and the MULT/DIV sign-extension bugs are real hardware behavior that software can observe and depend on. Implementing them “correctly” per the manual is the bug — see sra and mult. Each is pinned by a test that fails if it is “fixed”, so the intent survives a well-meaning future reader.

Structs

HiLo

The HI/LO register pair, written by every multiply and divide.

Enums

MulDiv

The multiply/divide family, for cost lookup.

Constants

MFHI_MFLO_HAZARD_INSTRUCTIONS

How many instructions after MFHI/MFLO must not write HI/LO.

Functions

add

ADD — 32-bit signed add, traps on overflow.

addu

ADDU — 32-bit add, no trap. The U means “unchecked”, not “unsigned”: the result is still sign-extended as a signed 32-bit value.

and

AND — bitwise and, full 64-bit.

dadd

DADD — 64-bit signed add, traps on overflow.

daddu

DADDU — 64-bit add, no trap.

ddiv

DDIV — 64-bit signed divide.

ddivu

DDIVU — 64-bit unsigned divide.

div

DIV — 32-bit signed divide. Reproduces the VR4300 sign-extension erratum.

divu

DIVU — 32-bit unsigned divide. No erratum applies.

dmult

DMULT — 64-bit signed multiply, full 128-bit result.

dmultu

DMULTU — 64-bit unsigned multiply, full 128-bit result.

dsll

DSLL — 64-bit shift left logical.

dsra

DSRA — 64-bit shift right arithmetic. sa is the effective 0..64 amount; see dsll on the DSRA/DSRA32 encoding split.

dsrl

DSRL — 64-bit shift right logical. sa is the effective 0..64 amount; see dsll on the DSRL/DSRL32 encoding split.

dsub

DSUB — 64-bit signed subtract, traps on overflow.

dsubu

DSUBU — 64-bit subtract, no trap.

lui

LUI — load upper immediate.

muldiv_stall_cycles

Pipeline stall in PCycles for a multiply or divide (UM Table 3-12).

mult

MULT — 32-bit signed multiply. Reproduces the VR4300 sign-extension erratum.

multu

MULTU — 32-bit unsigned multiply. Both operands are taken as their low 32 bits, zero-extended; no erratum applies.

nor

NOR — bitwise nor, full 64-bit. MIPS has no NOT; NOR rd, rs, $0 is it.

or

OR — bitwise or, full 64-bit.

sext32

Sign-extend a 32-bit result into the 64-bit register file.

sll

SLL — 32-bit shift left logical, result sign-extended.

slt

SLT — set on less than, signed 64-bit comparison.

sltu

SLTU — set on less than, unsigned 64-bit comparison.

sra

SRA — 32-bit shift right arithmetic. Reproduces the VR4300 erratum.

srl

SRL — 32-bit shift right logical, result sign-extended.

sub

SUB — 32-bit signed subtract, traps on overflow.

subu

SUBU — 32-bit subtract, no trap.

xor

XOR — bitwise exclusive or, full 64-bit.