Module pipeline 

The VR4300’s five-stage pipeline (ADR 0007).

IC → RF → EX → DC → WB (VR4300 User’s Manual §4.1, Figure 4-1): Instruction Cache fetch, Register Fetch, Execution, Data Cache fetch, Write Back. In-order, single-issue, with one architectural delay slot. At least 5 PCycles are required to execute an instruction, and up to five are in flight at once when the pipe flows.

Latches, not stages

Five stages have four boundaries, and the state lives on the boundaries. Latch is what travels with an instruction as it advances.

in_delay_slot riding in the latch rather than in a global CPU flag is load-bearing: a multi-cycle stall between a branch and its delay slot desynchronizes a global flag, and that is the classic bug in this area. With the flag attached to the instruction, Cause.BD and EPC come out right for free. delay_slot_flag_survives_a_multi_cycle_stall pins it.

Reverse step order is the latching

Pipeline::advance runs WB → DC → EX → RF → IC. Each stage reads its input latch and writes its output latch, so running downstream-first means a stage’s input still holds the previous cycle’s value when it is read. No value can therefore propagate two stages in one cycle, and no double buffering is needed — the reverse order is the latching.

This is a load-bearing invariant, not a style choice. Reversing it silently makes the pipeline one-cycle-too-fast; a_value_advances_exactly_one_stage_per_cycle is the guard.

Status

Structure only. The stages move latches and account for time; they do not decode or execute yet (T-11-002 onward). What is real here is the shape, the stall/interlock mechanism, the delay-slot carriage, and the interrupt gate — the parts that cannot be retrofitted later without rewriting every consumer.

Structs

Latch

State carried across one inter-stage boundary — what travels with an instruction as it advances.

Pipeline

The four inter-stage latches plus the pipeline control state.

Stall

A stall request: how long, and what caused it.

Enums

Exception

An aborting condition travelling down the pipe.

Interlock

The documented interlocks (UM Table 4-3).

Stage

The five pipeline stages, in hardware order (UM §4.1, Figure 4-1).

Functions

load_interlocks

Does a load into load_rt interlock with the following instruction?