Module cache 

The VR4300 primary caches (T-11-003).

Two direct-mapped, physically-tagged caches sit between the CPU and the bus: a 16 KiB instruction cache with 32-byte lines and an 8 KiB write-back data cache with 16-byte lines (UM §11.2, Tables 11-1/11-2).

Why they are modeled at all

They were a deliberate no-op until now (accuracy ledger D-5): with no cache contents, invalidate and write-back had nothing to act on, which is observationally sound only while nothing can observe staleness. That stops being true the moment a program writes a location through one path and reads it through another — which is precisely what n64-systemtest’s DCACHE: and ICACHE: groups do, and they are the reason this exists.

Indexing is PHYSICAL here, virtual on hardware

The real caches are virtually indexed and physically tagged, so two virtual addresses mapping to one physical address can occupy two lines (a cache alias). Indexing by physical address instead makes aliases impossible.

This is a deviation, not a simplification that is strictly safer. Software that observes aliasing — or that relies on an Index_* operation selecting a line by virtual index on a TLB-mapped page — sees different behavior here, because translation preserves only the low 12 bits while the D-cache index reaches bit 12 and the I-cache bit 13. What is bounded is the tested scope: every test that motivated this module operates through KSEG0, where the two indexings coincide. Accuracy ledger D-6.

TagLo

Index_Load_Tag and Index_Store_Tag move a line’s tag through COP0 TagLo, whose layout differs per cache (UM §5.3, Figures 5-19/5-20):

  bits 27..=8   PTagLo — the physical frame number, PA(31:12)
  bits  7..=6   PState — I-cache: 2 = Valid, 0 = Invalid
                         D-cache: 3 = Valid, 0 = Invalid

The D-cache’s write-back (“dirty”) bit is not in TagLo, so a clean and a dirty valid line are indistinguishable to Index_Load_Tag. That is hardware behavior, not an omission — see Dcache::load_tag.

Structs

Dcache

The 8 KiB write-back data cache.

Icache

The 16 KiB instruction cache.

Writeback

What a cache operation needs the caller to do on its behalf.

Constants

DCACHE_LINE

Data-cache line size, in bytes (UM §11.2).

DCACHE_LINES

Lines in the 8 KiB data cache.

ICACHE_LINE

Instruction-cache line size, in bytes (UM §11.2).

ICACHE_LINES

Lines in the 16 KiB instruction cache.