pub enum Exception {
}Expand description
An aborting condition travelling down the pipe.
Deliberately not called Fault. UM §4.5 defines a fault as the union of
interlocks and exceptions (Figure 4-11: Faults = Interlocks ∪ Exceptions,
split into Stalls vs Abort), and CEN64 follows that wider usage. What rides in
a latch here is only the aborting subset, so it carries the narrower name.
Variants§
Interrupt
An interrupt was accepted (Cause.IP unmasked, IE set, EXL/ERL clear).
AddressError
Address error on an instruction fetch or data access.
Carries the direction because the architecture does: AdEL (4) and
AdES (5) are different ExcCode values (UM Table 6-2, p. 172), and
a handler distinguishes them. An instruction fetch is a load.
Overflow
Integer overflow (ADD, ADDI, SUB, DADD, …).
Syscall
SYSCALL.
Breakpoint
BREAK.
Trap
A conditional trap (TGE, TEQ, TNEI, …) whose condition held.
ReservedInstruction
A reserved / unimplemented opcode.
CoprocessorReserved
A reserved encoding within a coprocessor’s instruction space.
Reports the same ExcCode as Exception::ReservedInstruction but
also sets Cause.CE to the coprocessor number. A plain
ReservedInstruction leaves CE at zero, so the two are not
interchangeable — n64-systemtest checks the whole Cause register, and
DCFC2 with CU2 set expects CE = 2.
CoprocessorUnusable
A coprocessor instruction with that unit disabled in Status.CU.
Nmi
Non-maskable interrupt (UM §6.4.6).
Not one of the Cause.ExcCode exceptions: it writes no Cause, saves to
ErrorEPC rather than EPC, sets ERL rather than EXL, and is taken
“regardless of the settings of the EXL, ERL, and the IE bits”. It rides
in this enum anyway so it can reuse the pipeline-flush machinery every
other exception uses; crate::exception::dispatch intercepts it before
any of the general path runs.
TlbRefill
A TLB refill — no entry matched. Takes the refill vector.
Fields
wide: boolThe access was made with 64-bit addressing enabled for its mode
(Status.KX/SX/UX), which selects the XTLB refill vector at
offset 0x080 instead of the 32-bit one at 0x000.
Carried on the exception rather than re-derived at dispatch because
by then EXL is set, which forces Pipeline::access_mode to
report Kernel and would answer for the handler’s mode instead of the
faulting access’s.
TlbInvalid
A TLB entry matched but was invalid. Takes the general vector, with
the same ExcCode as a refill — the vector is the only difference, which
is why they are separate variants rather than one with a flag nobody
reads.
TlbModified
A store to a valid but non-writable page.
FloatingPoint
A floating-point operation raised a condition whose FCSR.Enable bit is
set.
Carries nothing: which condition fired is reported in FCSR.Cause, not
in COP0 Cause, and the handler reads it from there. Adding a field
here would duplicate — and could contradict — the architectural record.