Enum Interlock 

pub enum Interlock {
    Ldi,
    Dcb,
    Dcm,
    Icb,
    Itm,
    Mci,
    Cop,
    Cp0i,
    Exception,
}

The documented interlocks (UM Table 4-3).

Held as a named enum rather than a bare cycle count so a stall is always attributable — “why did this stall” is answerable from a trace.

Variants

Ldi

Load interlock — 1 cycle (UM §4.6.5).

Deliberately imprecise, matching hardware: it fires when the next instruction’s rs or rt field equals the load’s rt, whether or not that field is actually used as a source. See load_interlocks.

Dcb

Data cache busy — a cached store keeps the cache busy for its DC and WB stages, so a following cache access stalls 1 cycle (UM §4.6.7).

Dcm

Data cache miss — the fill cost is 8..=9 + M PCycles (UM Table 11-1).

Icb

Instruction cache busy (UM §4.6.3).

Itm

Instruction micro-TLB miss — 3 PCycles (UM §4.6.2).

Mci

Multi-cycle interlock: MULT/DIV/FPU stall the whole pipeline for the documented count (UM Tables 3-12, 7-14).

Cop

Cache operation (UM Table 4-3).

Cp0i

CP0 bypass interlock — 1 PCycle (UM §4.6.9, p. 113).

Named but never raised. On hardware it fires when an instruction that caused an exception reaches WB while the next instruction in DC reads any CP0 register. Here, taking an exception already flushes the pipeline and stalls for the 2-PCycle epilogue, so the two triggers overlap and no case distinguishes them — charging this on top would invent a cycle the hardware may not spend. Separating them needs the timing set n64-systemtest ships default-off, the same instrument ledger C-1 waits on.

The variant stays because Interlock enumerates the documented taxonomy, and a gap in a taxonomy is worth more than a silently missing row. This doc previously said it fires, in the present tense, which is the comment-is-not-an-implementation hazard docs/engineering-lessons.md §3.3c describes – the cost was itself recorded as undocumented in three files while sitting in the very paragraph they cited (§3.3b).

Exception

Taking an exception — 2 PCycles (UM §4.7, p. 114).

Not strictly one of Table 4-3’s eight interlocks: the pipeline stalls while the epilogue runs and the aborted instructions drain. Named here so a trace can attribute the cycles rather than showing an unexplained gap.

Trait Implementations

impl Clone for Interlock

fn clone(&self) -> Interlock

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interlock

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'de> Deserialize<'de> for Interlock

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Hash for Interlock

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for Interlock

fn eq(&self, other: &Interlock) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for Interlock

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Copy for Interlock

impl Eq for Interlock

impl StructuralPartialEq for Interlock