pub struct Latch {
pub occupied: bool,
pub pc: u64,
pub word: u32,
pub in_delay_slot: bool,
pub abort: Option<Exception>,
pub decoded: Decoded,
pub rs_val: u64,
pub rt_val: u64,
pub write_back: WriteBack,
pub mem: Option<MemOp>,
pub cop0: Option<Cop0Access>,
}Expand description
State carried across one inter-stage boundary — what travels with an instruction as it advances.
Fields§
§occupied: boolIs an instruction present at this boundary? A bubble is false.
pc: u64The PC of the instruction in flight.
word: u32The raw instruction word (decode is T-11-002).
in_delay_slot: boolIs this instruction in a branch delay slot?
Travels with the instruction, never as global CPU state — that is the whole point (see the module docs).
abort: Option<Exception>An aborting condition stamped into this latch and every latch upstream.
decoded: DecodedThe decoded instruction, filled at IC.
rs_val: u64rs value, read at RF.
rt_val: u64rt value, read at RF.
write_back: WriteBackWhat EX computed, committed at WB.
mem: Option<MemOp>A memory access EX resolved for DC to perform.
cop0: Option<Cop0Access>A COP0 access EX resolved: read performed in DC, write in WB.
Split across those two stages because UM §4.6.9 defines the CP0 bypass
interlock in terms of a write reaching WB while the next instruction
reads in DC — a rule that cannot be expressed if both happen in EX.