Module fpu 

FPU arithmetic (T-13-002).

Pure functions over IEEE-754 values, with the VR4300’s FCSR semantics layered on top. Kept separate from crate::fpr (the register file) and crate::cop1 (the control registers) so each can be tested without the others.

Rounding

FCSR.RM selects the mode (UM §7.2.4): 0 nearest-even, 1 toward zero, 2 toward +∞, 3 toward −∞.

Every operation here honors it, arithmetic included. The four arithmetic operations are adapters over crate::softfloat, which takes the mode as a parameter and rounds exactly once; the conversions take a Rounding directly.

This paragraph has been wrong in both directions and is worth reading carefully before it is edited again. It first claimed the modes applied throughout while the arithmetic ignored them; it was then corrected to say the arithmetic could not honor them, which became false when the soft-float path landed. See docs/engineering-lessons.md §3.3c — the rule is that a comment asserting what the code does goes stale silently, because no test fails when it is wrong.

What is deliberately absent

The FP multiplication erratum is not here. It is a property of specific early console revisions (n64brew_wiki/markdown/VR4300.md) and belongs with the revision model, not with the arithmetic; implementing it inline would make every multiply on every console wrong.

Structs

Flags

The FCSR cause/flag bits an operation can raise (UM §7.2.2).

Outcome

A result plus the flags producing it raised.

Enums

Relation

The outcome of an ordered comparison: which of the three mutually exclusive relations holds.

Rounding

The rounding mode from FCSR.RM (UM §7.2.4).

Stepping

Which VR4300 stepping a console carries.

Constants

CAUSE_MASK

FCSR.Cause — bits 17:12, the field an operation replaces wholesale.

CAUSE_UNIMPLEMENTED

The Unimplemented Operation cause bit (FCSR bit 17).

FMT_D

fmt for double precision.

FMT_L

fmt for 64-bit fixed point (L).

FMT_S

fmt for single precision, as the COP1 encoding gives it.

FMT_W

fmt for 32-bit fixed point (W), the source format of CVT.fmt.W.

Functions

abs_d

ABS.D.

abs_s

ABS.S — clears the sign bit.

add_d

ADD.D.

add_s

ADD.S.

arith_unimplemented_d

See arith_unimplemented_s.

arith_unimplemented_s

Do these arithmetic operands force unimplemented operation before the operation is even attempted?

compare_d

C.cond.fmt — compare two double-precision values.

compare_s

C.cond.fmt — compare two single-precision values.

cvt_d_s

CVT.D.S — single to double. Always exact: every f32 is an f64.

cvt_s_d

CVT.S.D — double to single. Can overflow, underflow or lose precision.

delay_cycles

Pipeline cycles for a COP1 arithmetic instruction — UM Table 7-14.

div_d

DIV.D.

div_s

DIV.S.

flush_subnormal_f32

Flush a subnormal result to zero or to the smallest normal, per FCSR.FS.

flush_subnormal_f64

See flush_subnormal_f32.

is_snan_f32

Is this f32 a signaling NaN as the VR4300 classifies one?

is_snan_f64

Is this f64 a signaling NaN as the VR4300 classifies one?

is_subnormal_f32

Is this a subnormal — a non-zero value with a zero exponent field?

is_subnormal_f64

Is this f64 a subnormal? See is_subnormal_f32.

is_unimplemented_nan_f32

Is this a NaN the VR4300’s arithmetic cannot handle?

is_unimplemented_nan_f64

See is_unimplemented_nan_f32.

long_convertible

Does a 64-bit integer satisfy CVT.[S,D].L’s range restriction?

mul_d

MUL.D.

mul_erratum_triggers

Would the erratum’s trigger condition fire for this multiply?

mul_s

MUL.S.

neg_d

NEG.D.

neg_s

NEG.S — flips the sign bit.

round_f64

Round a float to an integer under an explicit Rounding mode.

stall_cycles

The stall a COP1 arithmetic instruction adds, in PCycles.

sub_d

SUB.D.

sub_s

SUB.S.

to_i32

Convert a float to a 32-bit integer under mode.

to_i64

Convert a float to a 64-bit integer under mode.