pub enum Stage {
Ic,
Rf,
Ex,
Dc,
Wb,
}Expand description
The five pipeline stages, in hardware order (UM §4.1, Figure 4-1).
Note the names: IC and DC, not IF/DF. The manual’s whole interlock
and exception taxonomy is stated stage-relative, so these spellings are what
make a citation resolvable.
Variants§
Ic
Instruction Cache fetch.
Rf
Register Fetch.
Ex
Execution.
Dc
Data Cache fetch — the bus access, and where interrupts are sampled.
Wb
Write Back.
Trait Implementations§
Source§impl<'de> Deserialize<'de> for Stage
impl<'de> Deserialize<'de> for Stage
Source§fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
Deserialize this value from the given Serde deserializer. Read more
impl Copy for Stage
impl Eq for Stage
impl StructuralPartialEq for Stage
Auto Trait Implementations§
impl Freeze for Stage
impl RefUnwindSafe for Stage
impl Send for Stage
impl Sync for Stage
impl Unpin for Stage
impl UnsafeUnpin for Stage
impl UnwindSafe for Stage
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more