Module armv3 

The ARMv3 (ARM6-class, pre-Thumb) CPU core — ST018’s LLE engine.

ST018 is Hayazashi Nidan Morita Shogi 2’s coprocessor; see board’s doc for the detection research — an earlier version of this doc wrongly attributed this chip to Star Ocean, which uses S-DD1 only, no ARM chip.

Clean-room port of Mesen2’s ArmV3Cpu (MIT, Core/SNES/Coprocessors/ST018/ArmV3Cpu.cpp) — chosen over ares’ sfc/coprocessor/armdsp, which instead reuses ares’ generic shared component/processor/arm7tdmi (a full ARM+Thumb ARM7TDMI superset the real ST018 chip, an ARMv3/ARM6-class part that predates Thumb, never needed). Mesen2’s dedicated ArmV3Cpu is the more faithful, more focused scope. Full architecture notes (register banking, the pipeline’s PC+8 timing, every instruction’s documented hardware quirks, the board bus protocol) live in docs/st018-arm-notes.md, kept in sync with this module as it’s built out.

Built bottom-up, in the order docs/st018-arm-notes.md lays out:

1. primitives — the barrel shifter, condition codes, ALU core (pure functions, no state).
2. regs — the register file, mode-switch banking, and the 3-stage pipeline model.
3. bus + cpu — the full instruction set: data processing, branch, MSR/MRS, exception entry, LDR/STR, LDM/STM, multiply/multiply-long, and SWP/SWPB.
4. board — the SNES-side board wrapper, wired into board::select.

Re-exports

pub use board::St018Board;

pub use bus::ArmBus;

pub use cpu::Cpu;

pub use primitives::Flags;

pub use primitives::add;

pub use primitives::check_condition;

pub use primitives::logical_flags;

pub use primitives::rotate_right;

pub use primitives::rotate_right_carry;

pub use primitives::shift_asr;

pub use primitives::shift_lsl;

pub use primitives::shift_lsr;

pub use primitives::shift_ror;

pub use primitives::shift_rrx;

pub use primitives::sub;

pub use regs::Cpsr;

pub use regs::Mode;

pub use regs::Pipeline;

pub use regs::Regs;

Modules

board

The ST018 board — the ARMv3 (ARM6) coprocessor wired into a cartridge.

bus

The host-facing memory surface the ARM core reads/writes through (mirrors the Hg51bBus/rustysnes_cpu::Bus pattern already used elsewhere in this codebase).

cpu

Instruction decode/execute for the ARMv3 core.

primitives

Pure, state-free ARM primitives: the barrel shifter, condition codes, and the ALU core.

regs

The ARM register file (with mode banking) and the 3-stage instruction pipeline.