rustysnes_cart/coproc/armv3/mod.rs
1//! The ARMv3 (ARM6-class, pre-Thumb) CPU core — ST018's LLE engine.
2//!
3//! ST018 is Hayazashi Nidan Morita Shogi 2's coprocessor; see [`board`]'s doc for the detection
4//! research — an earlier version of this doc wrongly attributed this chip to Star Ocean, which
5//! uses S-DD1 only, no ARM chip.
6//!
7//! Clean-room port of Mesen2's `ArmV3Cpu` (MIT, `Core/SNES/Coprocessors/ST018/ArmV3Cpu.cpp`) —
8//! chosen over ares' `sfc/coprocessor/armdsp`, which instead reuses ares' generic shared
9//! `component/processor/arm7tdmi` (a full ARM+Thumb ARM7TDMI superset the real ST018 chip, an
10//! ARMv3/ARM6-class part that predates Thumb, never needed). Mesen2's dedicated `ArmV3Cpu` is the
11//! more faithful, more focused scope. Full architecture notes (register banking, the pipeline's
12//! PC+8 timing, every instruction's documented hardware quirks, the board bus protocol) live in
13//! `docs/st018-arm-notes.md`, kept in sync with this module as it's built out.
14//!
15//! Built bottom-up, in the order `docs/st018-arm-notes.md` lays out:
16//! 1. [`primitives`] — the barrel shifter, condition codes, ALU core (pure functions, no state).
17//! 2. [`regs`] — the register file, mode-switch banking, and the 3-stage pipeline model.
18//! 3. [`bus`] + [`cpu`] — the full instruction set: data processing, branch, MSR/MRS, exception
19//! entry, `LDR`/`STR`, `LDM`/`STM`, multiply/multiply-long, and `SWP`/`SWPB`.
20//! 4. [`board`] — the SNES-side board wrapper, wired into `board::select`.
21
22pub mod board;
23pub mod bus;
24pub mod cpu;
25pub mod primitives;
26pub mod regs;
27
28pub use board::St018Board;
29pub use bus::ArmBus;
30pub use cpu::Cpu;
31pub use primitives::{
32 Flags, add, check_condition, logical_flags, rotate_right, rotate_right_carry, shift_asr,
33 shift_lsl, shift_lsr, shift_ror, shift_rrx, sub,
34};
35pub use regs::{Cpsr, Mode, Pipeline, Regs};