Expand description
Instruction decode/execute for the ARMv3 core.
Ties crate::coproc::armv3::regs’s register file and pipeline together with the
crate::coproc::armv3::bus::ArmBus trait and drives them one instruction at a time (Mesen2
ArmV3Cpu::Exec/InitArmOpTable and friends).
Status: the full ARMv3 instruction set is implemented — data processing, branch, MSR/MRS,
exception entry, LDR/STR, LDM/STM, MUL/MLA/MULL/MLAL, and SWP/SWPB. Only the
SNES-side board wrapper (firmware loading, the master-clock catch-up loop, the handshake
registers) and its board::select wiring remain (docs/st018-arm-notes.md tracks the
remaining build order).
Structs§
- Cpu
- The full ARMv3 core: register file, pipeline, and instruction execution.
Enums§
- Vector
- Which real ARM exception vector an entry lands at (Mesen2
ArmV3CpuVector).