Module regs 

The ARM register file (with mode banking) and the 3-stage instruction pipeline.

Clean-room port of the relevant pieces of Mesen2’s ArmV3Cpu/ArmV3CpuState (see the parent module doc). This is step 2+3 of the build order in docs/st018-arm-notes.md: register banking and the pipeline’s implicit “PC reads as address+8” timing, both landed before any instruction decode/execute exists (nothing here depends on it, and the pipeline model is the single highest-risk fidelity point every later instruction depends on getting right).

Modules

mode

The 7 real ARM processor modes.

Structs

Cpsr

The full CPSR (or an SPSR): mode + interrupt-mask bits + the Flags condition codes.

Insn

One fetched-but-not-yet-executed instruction word, tagged with the address it was fetched from (Mesen2 ArmV3InstructionData).

Pipeline

The 3-stage Fetch/Decode/Execute pipeline (Mesen2 ArmV3CpuPipeline).

Regs

The ARM register file: R0-R15 plus every mode’s banked registers and SPSR.

Type Aliases

Mode

A u8-backed ARM mode value — see the mode module for the 7 real constants and the fallback-to-User/System posture for anything else.