pub struct Pipeline {
pub fetch: Insn,
pub decode: Insn,
pub execute: Insn,
/* private fields */
}Expand description
The 3-stage Fetch/Decode/Execute pipeline (Mesen2 ArmV3CpuPipeline).
This is the ENTIRE mechanism behind ARM’s well-known “PC reads as address+8” quirk: r15
(owned by Regs, threaded through Self::process rather than duplicated here) tracks the
FETCH stage’s address, two stages ahead of whatever instruction is currently in Execute. No
+8 constant exists anywhere in this port — it falls straight out of this stage timing, which
is exactly why getting this model right BEFORE porting any instruction that reads R15 as an
operand matters (see docs/st018-arm-notes.md’s pipeline section).
Bus-side access-mode bits (Sequential/Word/Byte/Prefetch, used by the board wrapper for
its own cycle-timing bookkeeping) are deliberately NOT modeled here yet — they don’t affect
address/opcode sequencing, only the caller’s read_code timing side effects, and land with
the board wrapper (docs/st018-arm-notes.md step 9).
Fields§
§fetch: InsnThe most recently fetched, not-yet-decoded word.
decode: InsnThe word decoded on the prior step, about to become execute on the next one.
execute: InsnThe instruction actually running on the current step.
Implementations§
Source§impl Pipeline
impl Pipeline
Sourcepub const fn request_reload(&mut self)
pub const fn request_reload(&mut self)
Request a full pipeline flush + refill on the next Self::process call — set whenever
an instruction writes R15 (a taken branch, a data-processing MOV PC, ..., an LDR PC, ..., an exception entry, etc.). Not yet wired to any register-write path (that lands with
instruction execute); exposed now so the pipeline model itself is independently testable.
Sourcepub fn process(&mut self, r15: &mut u32, read_code: impl FnMut(u32) -> u32)
pub fn process(&mut self, r15: &mut u32, read_code: impl FnMut(u32) -> u32)
Advance the pipeline by one stage (Mesen2 ProcessPipeline): reload first if requested,
then unconditionally shift Execute←Decode←Fetch←(a fresh fetch at r15+4). Call this once
per CPU step, AFTER the current Execute-stage instruction has run.