Struct Cpu 

pub struct Cpu {
    pub regs: Regs,
    pub pipeline: Pipeline,
}

The full ARMv3 core: register file, pipeline, and instruction execution.

Fields

regs: Regs

The register file (R0-R15, mode-banked, plus CPSR/SPSRs).

pipeline: Pipeline

The 3-stage Fetch/Decode/Execute pipeline.

Implementations

impl Cpu

pub fn power_on(&mut self, bus: &mut impl ArmBus)

Power on (or reset) the core (Mesen2 PowerOn): zero every register, enter Supervisor mode with both interrupt lines masked, and prime the pipeline from address 0 (the ARM reset vector). Unlike PowerOn(forReset=true), this does not preserve a cycle counter — the board wrapper (not yet built) owns cycle-count bookkeeping, not the core itself.

pub fn step(&mut self, bus: &mut impl ArmBus)

Execute the instruction currently in the Execute pipeline stage (if its condition holds), then advance the pipeline (Mesen2 Exec). Call once per CPU cycle-step.

Trait Implementations

impl Clone for Cpu

fn clone(&self) -> Cpu

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cpu

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cpu

fn default() -> Cpu

Returns the “default value” for a type.

impl Copy for Cpu