Struct Regs 

pub struct Regs {
    pub r: [u32; 16],
    pub cpsr: Cpsr,
    /* private fields */
}

The ARM register file: R0-R15 plus every mode’s banked registers and SPSR.

Banking follows real ARM hardware (and Mesen2’s SwitchMode) exactly: R8-R12 are shared by every mode EXCEPT FIQ (which gets its own private R8-R12); R13/R14 are banked separately per mode, INCLUDING a distinct “User” bank from the four privileged non-FIQ modes’ banks. This project’s other CPU cores don’t need this pattern (the 65C816 and SA-1 have no register banking), so it has no existing precedent to crib the shape from — ported straight from the reference memcpy-based save/restore sequence as explicit slice copies.

Fields

r: [u32; 16]

R0-R15 (R15 = PC) — the currently-banked-in view every instruction reads/writes.

cpsr: Cpsr

The live CPSR (current mode + interrupt masks + condition flags).

Implementations

impl Regs

pub fn switch_mode(&mut self, new_mode: Mode)

Switch the active processor mode, banking R8-R14 in/out exactly like real ARM hardware (Mesen2 SwitchMode).

new_mode is masked to its real 5-bit hardware width THEN OR’d with mode::BIT unconditionally (bit 4 is always set on real hardware — every caller, including MSR’s raw mode field, relies on this rather than validating it themselves). The mask keeps self.cpsr.mode a clean 5-bit value everywhere it’s read (in particular Cpsr::to_u32’s packed layout, where a stray high bit would corrupt the adjacent interrupt-mask/reserved bits) even if some future caller passes an unmasked byte. A no-op if the mode is already active (matches the source’s early-return, and avoids a redundant full 7-register bank round-trip on every same-mode MSR).

pub const fn spsr(&self) -> Cpsr

The current mode’s SPSR (Mesen2 GetSpsr). User/System (and any unrecognized mode, matching the source’s default: fallback) have no real SPSR; reading/writing it there is architecturally UNPREDICTABLE, and this port follows the source’s own choice of aliasing the live CPSR itself as a harmless, safe fallback rather than inventing new behavior.

pub const fn spsr_mut(&mut self) -> &mut Cpsr

Mutable access to the current mode’s SPSR — see Self::spsr.

Trait Implementations

impl Clone for Regs

fn clone(&self) -> Regs

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Regs

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Regs

fn default() -> Regs

Returns the “default value” for a type.

impl PartialEq for Regs

fn eq(&self, other: &Regs) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Regs

impl Eq for Regs

impl StructuralPartialEq for Regs