Module coproc 

On-cart coprocessors that plug into the crate::board::Board trait.

The headline economy of the SNES coprocessor breadth (docs/cart.md, docs/adr/0003) is the shared NEC DSP engine: one upd77c25::Upd77c25 LLE core backs DSP-1/2/3/4 + ST010/011 (six chips), parameterized only by firmware + register widths. Phase 4 lands DSP-1 (dsp1::Dsp1Board, Core/Curated); the BestEffort siblings reuse the same engine in Phase 7.

Phase 4’s second Core/Curated coprocessor is the Super FX / GSU (superfx::SuperFxBoard over the gsu::Gsu Argonaut RISC core). Unlike the DSP family it carries no chip-ROM dump — the GSU program lives in the cartridge ROM — so it is functional the moment the cart loads. It reuses the same host-sync idea: the GSU runs to completion the instant the CPU sets the Go flag, so no free-running core-scheduler tick is needed.

Phase 4’s third Core/Curated coprocessor is the SA-1 (sa1::Sa1Board) — a second WDC 65C816 @ ~10.74 MHz plus a support ASIC. Like Super FX it carries no chip-ROM dump (the SA-1 program is in the cartridge ROM). Unlike the host-sync chips it is a real parallel CPU: this board owns the entire SA-1 system (registers, Super-MMC banking, BW-RAM, I-RAM, arithmetic unit, DMA, var-len, H/V timer) and exposes the SA-1 CPU’s memory view via the Board second-CPU hooks; rustysnes-core instantiates and steps the second CPU (the crate graph forbids rustysnes-cart from depending on rustysnes-cpu).

Re-exports

pub use armv3::St018Board;

pub use cx4::Cx4Board;

pub use dsp1::Dsp1Board;

pub use epsonrtc::EpsonRtc;

pub use gsu::Gsu;

pub use hg51b::Hg51b;

pub use hg51b::Hg51bBus;

pub use necdsp_variant::NecDspVariantBoard;

pub use necdsp_variant::Variant as NecDspVariant;

pub use obc1::Obc1Board;

pub use sa1::Sa1Board;

pub use sdd1::Sdd1Board;

pub use sharprtc::SharpRtcBoard;

pub use spc7110::Spc7110Board;

pub use superfx::SuperFxBoard;

pub use upd77c25::Revision;

pub use upd77c25::Upd77c25;

Modules

armv3

The ARMv3 (ARM6-class, pre-Thumb) CPU core — ST018’s LLE engine.

cx4

The CX4 board — the Hitachi HG51B169 wired into a LoROM cartridge (Mega Man X2, Mega Man X3).

dsp1

The DSP-1 board — the µPD77C25 wired into a LoROM/HiROM cartridge.

epsonrtc

The Epson RTC-4513 real-time clock — the second ASIC on the one commercial cart that pairs it with SPC7110 (Far East of Eden Zero / Tengai Makyou Zero).

gsu

The GSU (Argonaut RISC) — the Super FX coprocessor core.

hg51b

The Hitachi HG51B S169 core — the CX4 coprocessor’s CPU (Mega Man X2, Mega Man X3).

necdsp_variant

Single-game NEC DSP variant boards — DSP-2, DSP-4, ST010.

obc1

The OBC1 board — a simple sprite-object-controller ASIC (Metal Combat: Falcon’s Revenge).

sa1

The SA-1 board — the Super Accelerator system (a second 65C816 + ASIC) on the cartridge.

sdd1

The S-DD1 board — Nintendo’s lossless decompression ASIC (Star Ocean, Street Fighter Alpha 2).

sharprtc

The Sharp S-RTC standalone real-time clock — the only commercial cart is Daikaijuu Monogatari II (an ExHiROM title; ares board EXHIROM-RAM-SHARPRTC).

spc7110

The SPC7110 board — Hudson’s decompression + memory-mapping ASIC (Far East of Eden Zero / Tengai Makyou Zero).

superfx

The Super FX board — the GSU wired into a LoROM cartridge.

upd77c25

The NEC µPD77C25 / µPD96050 LLE engine — the shared NEC DSP core.