pub const fn shift_ror(value: u32, shift: u8, carry: bool) -> (u32, bool)Expand description
ROR (rotate right) by a register-derived amount 0..=255 (Mesen2 ShiftRor).
The rotate amount is first reduced mod 32 (shift & 0x1F); if that reduction is itself 0
(i.e. the original amount was a nonzero multiple of 32), value is left UNCHANGED but carry
still becomes bit 31 of value — a real, easy-to-miss ARM ARM special case, ported exactly
as Mesen2 encodes it (the inner if shift != 0 only guards the rotate, not the carry
update). See shift_lsl for the shared outer shift == 0 no-op contract (the ORIGINAL,
pre-mask amount — distinct from the inner post-mask check).