Expand description
Pure, state-free ARM primitives: the barrel shifter, condition codes, and the ALU core.
The barrel shifter, the condition-code checker, and the Add/Sub/logical-op ALU core — each
verified against the ARM Architecture Reference Manual’s own documented truth tables. See the
parent module (coproc::armv3) doc for the full picture.
Structs§
- Flags
- The four ARM condition-code flags (CPSR bits 31-28 / N,Z,C,V).
Functions§
- add
- ARM
ADD-family:op1 + op2 + carry_in. - check_
condition - Evaluate a 4-bit ARM condition code against the current flags (Mesen2
CheckConditions). - logical_
flags - ARM logical-op flag update (
AND/EOR/ORR/MOV/BIC/MVN/TST/TEQ, Mesen2LogicalOp). - rotate_
right RORby a fixed 1-31 amount with no carry-out tracking (Mesen2’s 2-argumentRotateRight).- rotate_
right_ carry RORby a0..=31amount, also returning the carry-out (bitshift-1ofvalue) — Mesen2’s 3-argumentRotateRight, used byArmDataProcessing’s immediate-operand rotate.- shift_
asr ASR(arithmetic shift right, sign-extending) by a register-derived amount0..=255.- shift_
lsl LSL(logical shift left) by a register-derived amount0..=255(Mesen2ShiftLsl).- shift_
lsr LSR(logical shift right) by a register-derived amount0..=255(Mesen2ShiftLsr). Seeshift_lslfor the sharedshift == 0no-op contract.- shift_
ror ROR(rotate right) by a register-derived amount0..=255(Mesen2ShiftRor).- shift_
rrx RRX(rotate right extended by 1, through the carry flag; Mesen2ShiftRrx).- sub
- ARM
SUB-family:Add(op1, !op2, carry_in, ...).