Crate rustysnes_core 

rustysnes-core — the Bus + the master-clock lockstep scheduler. The single crate that knows about every chip; it re-exports their public types so downstream consumers depend on rustysnes-core, not the chip crates directly.

Re-exports

pub use bus::Bus;

pub use scheduler::System;

pub use rustysnes_apu as apu;

pub use rustysnes_cart as cart;

pub use rustysnes_cpu as cpu;

pub use rustysnes_ppu as ppu;

Modules

bus

The Bus owns everything mutable.

cheat

SNES cheat-code decoding: Game Genie and Pro Action Replay (v0.8.0 "Instrumentation", T-81-003).

controller

SNES controller-port peripherals beyond the standard gamepad: Mouse, Super Scope, and Super Multitap (v0.9.0, Phase 7’s “niche peripherals” exit criterion).

dma

GP-DMA + HDMA — the 8-channel DMA controller ($420B/$420C, $43n0-$43nA).

dma_bus

The narrow bus interface the DMA controller drives.

facade

The pure emulation-core facade: load a ROM, step a frame, expose the framebuffer + audio.

movie

TAS movie record/playback — a deterministic input log plus a System::save_state-compatible start point.

sa1_bus

The SA-1 CPU’s bus adapter — the bridge that lets rustysnes-core step the second 65C816.

scheduler

The master-clock lockstep scheduler — the run loop that owns the CPU + Bus.