Expand description
The Bus owns everything mutable.
It holds the PPU1/PPU2, the SPC700+S-DSP, the cart (→ board / coprocessor), WRAM,
controllers, the open-bus latch, the CPU-side registers ($4200-$421F), the mul/div unit,
and the DMA/HDMA controller. The 65C816 borrows &mut Bus during an instruction; the PPU and
DMA see narrower bus traits (rustysnes_ppu::VideoBus, crate::dma_bus::DmaBus)
implemented on this same struct. The APU owns its ARAM/DSP internally; the Bus drives it
through [rustysnes_apu::Apu] directly — the four $2140-$2143 port latches via
[rustysnes_apu::Apu::cpu_read_port]/[rustysnes_apu::Apu::cpu_write_port] and the SPC clock
via [rustysnes_apu::Apu::advance_smp_cycle] (the integer-accumulator async resync).
§The master clock lives here
The SNES CPU cycle is 6, 8, or 12 master clocks depending on the address region (and the
FastROM bit). The CPU asks the Bus for the access cost via CpuBus::access_cycles (ares
wait) and drives the clock with CpuBus::advance (ares step), sequencing the advance
around each CpuBus::read24/CpuBus::write24 so the access lands at the hardware-exact
instant — a write at the end of its cycle, a read four clocks before it. Each master-clock
advance steps the PPU dot clock (4 master/dot) and the SPC accumulator in lockstep, so a
mid-instruction PPU event (an HV-IRQ at a precise dot, a mid-scanline register write seen at
the right hcounter) lands at the right time without per-quirk patches.