Crate rustysnes_cpu 

rustysnes-cpu — WDC 65C816 (cpu).

16-bit 65C816 main CPU; emulation/native modes; region-variable (FastROM/SlowROM) access speed. The CPU borrows &mut impl Bus for the duration of an instruction (the RustyNES “Bus owns everything mutable” rule — the CPU never owns the PPU/APU/cart). The concrete Bus impl lives in rustysnes-core; this crate only sees the narrow Bus trait.

Part of the one-directional chip-crate graph (see docs/architecture.md): this crate does NOT depend on the other chip crates. #![no_std] + alloc so it cross-compiles to a bare-metal target; only the frontend carries std + unsafe.

Cycle-count unit

Cpu::step returns a count of CPU cycles (one per bus byte access plus internal I/O cycles the instruction consumed), per the standard 65C816 timing tables and the variable-timing rules in docs/cpu.md. It does not apply the per-access master-clock speed weighting (6/8/12) — the CPU asks the Bus for that via Bus::access_cycles and drives it with Bus::advance. The value equals the increment of Cpu::cycles across the call.

Re-exports

pub use addr::Effective;

pub use addr::Mode;

pub use bus::Bus;

pub use regs::Regs;

pub use regs::Status;

Modules

addr

Addressing-mode resolution for the 65C816.

bus

The CPU-side bus trait — the SNES port of RustyNES’s rustynes-cpu::Bus.

disasm

A minimal 65C816 disassembler for human-facing debug output.

exec

Instruction fetch / decode / execute for the 65C816, plus bus plumbing.

regs

WDC 65C816 register file and processor-status flags.

vectors

Native-mode interrupt/exception vector addresses (bank 0).

Structs

Cpu

WDC 65C816 CPU core.