rustysnes_core/lib.rs
1//! `rustysnes-core` — the Bus + the master-clock lockstep scheduler. The single crate that
2//! knows about every chip; it re-exports their public types so downstream consumers depend
3//! on `rustysnes-core`, not the chip crates directly.
4
5#![cfg_attr(not(feature = "std"), no_std)]
6extern crate alloc;
7
8pub mod bus;
9pub mod cheat;
10pub mod controller;
11pub mod dma;
12pub mod dma_bus;
13// The pure emulation-core facade (`load_rom`/`run_frame`/`framebuffer`/`save_state`/…), relocated
14// here from `rustysnes-frontend::emu` (`v1.2.0`) so a libretro core or any other headless embedder
15// can depend on this crate alone instead of the winit/wgpu/cpal/egui-heavy frontend. `std`-only
16// (needs `zip` archive extraction) — vanishes entirely from the `no_std` build.
17#[cfg(feature = "std")]
18pub mod facade;
19pub mod movie;
20pub mod sa1_bus;
21pub mod scheduler;
22// `v0.8.0`, T-81-001b: 65C816 read/write watchpoints. Compiled out entirely when `debug-hooks` is
23// off, so a default build carries zero extra code — this module's own doc has the detail.
24#[cfg(feature = "debug-hooks")]
25pub mod watchpoint;
26
27// Re-export the chip crates (the public surface).
28pub use rustysnes_apu as apu;
29pub use rustysnes_cart as cart;
30pub use rustysnes_cpu as cpu;
31pub use rustysnes_ppu as ppu;
32
33pub use bus::Bus;
34pub use scheduler::System;