Module dma 

GP-DMA + HDMA — the 8-channel DMA controller ($420B/$420C, $43n0-$43nA).

Clean-room port of the ares (ISC, vendor-ok) sfc/cpu/dma.cpp transfer model; never a verbatim copy. The DMA controller moves bytes between the A-bus (the 24-bit CPU address space) and the B-bus (the PPU/APU register window $2100-$21FF). Two flavors:

• GP-DMA (MDMAEN $420B): writing a non-zero mask runs every selected channel to completion with the CPU fully halted, 8 master clocks per byte (+ per-channel and alignment overhead). Cannot cross a bank (sourceAddress wraps in-bank).
• HDMA (HDMAEN $420C): per visible scanline, fires at H≈$116; each active channel transfers its line entry (direct or indirect), 8 clocks/byte plus overhead, and HDMA preempts an in-flight GP-DMA.

The controller never touches the concrete Bus directly: it drives the DmaBus trait so it stays decoupled (and unit-testable in isolation). The master-clock cost is reported back to the caller (the scheduler advances the clock by it).

Structs

Channel

One of the 8 DMA channels ($43n0-$43nA).

Dma

The 8-channel DMA controller plus the MDMAEN/HDMAEN enables.