Expand description
The SA-1 CPU’s bus adapter — the bridge that lets rustysnes-core step the second 65C816.
The one-directional crate graph forbids rustysnes-cart from depending on rustysnes-cpu, so
the SA-1 system (registers, Super-MMC banking, BW-RAM, I-RAM, arithmetic unit, DMA, timer)
lives in [rustysnes_cart::coproc::sa1] and exposes the SA-1 CPU’s memory view through the
[rustysnes_cart::Board] second-CPU hooks. This adapter wraps the cart board behind the
[rustysnes_cpu::Bus] trait so the second [rustysnes_cpu::Cpu] (owned by the scheduler) can
borrow it for an instruction.
Unlike the main bus this adapter does not advance the master clock: the SA-1’s own timing is
driven by the scheduler, which charges the SA-1 H/V timer from the instruction’s returned cycle
count (docs/scheduler.md §SA-1). Interrupt/reset vector redirection (the SA-1 uses its own
CRV/CIV/CNV vectors, not the ROM $FFEx vectors) is handled inside the board’s
[rustysnes_cart::Board::second_cpu_read].