Crate rustysnes_ppu 

rustysnes-ppu — PPU1 (5C77) + PPU2 (5C78) (video).

Dual-chip PPU: BG modes 0-7 (incl. Mode 7 affine), OAM sprites, the dot-clock timeline. The PPU owns its own VRAM (64 KiB), CGRAM (palette), and OAM. Anything that has to reach the cartridge — Mode 7 / extended-bank reads on coprocessor boards, board IRQ/scanline notifies — goes through the narrow VideoBus trait, whose only concrete impl in production is the cart-mediated router in rustysnes-core. This is the RustyNES PpuBus shape, ported: the video chip depends ONLY on rustysnes-cart (its memory bus).

Part of the one-directional chip-crate graph (see docs/architecture.md): this crate does NOT depend on the cpu/apu chip crates. #![no_std] + alloc so it cross-compiles to a bare-metal target; only the frontend carries std + unsafe.

Timing convention

Per docs/scheduler.md (binding): RustySNES counts 341 dots of nominally 4 master clocks per line; the scheduler advances the PPU one dot at a time via Ppu::tick_dot. H runs 0..=339 (340 wraps to a new line), V runs 0..=261 (NTSC) / 0..=311 (PAL). Active output is dots 22..=277 on lines 1..=224 (1..=239 overscan); VBlank asserts at V=225 (V=240 overscan). The renderer is per-scanline (it composites a whole visible line at RENDER_DOT, one dot before that line’s own per-line HDMA run can observe/mutate the registers the composite reads), which is far simpler than a per-dot renderer and bit-identical to one for every currently-modeled case, including a per-line HDMA-driven register write (e.g. a raster scroll split) — which only becomes visible starting the following line, matching real hardware (docs/ppu.md §Mid-scanline/HDMA-driven register timing, landed v0.8.0).

Rendering note (clean-room)

The register semantics and rendering math here are re-implemented from docs/ppu.md plus the documented SNES hardware behavior (SNESdev/Fullsnes), structurally informed by the ares (ISC) PPU. No source was copied/ported verbatim.

Re-exports

pub use bus::VideoBus;

Modules

bus

The PPU-side narrow bus trait — the SNES port of RustyNES’s PpuBus.

Structs

Ppu

PPU1 (5C77) + PPU2 (5C78) state.

Enums

Region

Video region — fixes the line count and the NTSC/PAL status bit. Data, not behavior.

Constants

DOTS_PER_LINE

Dots per scanline (the RustySNES convention: 341 dots of nominally 4 master clocks).

FRAMEBUFFER_LEN

Framebuffer length at normal (non-hires) resolution, in 15-bit BGR pixels.

MASTER_CLOCKS_PER_DOT

Master clocks per PPU dot (nominal). The scheduler owns the long-dot remainder; this crate just counts dots. See docs/scheduler.md “Convention (binding)”.

MAX_SCREEN_WIDTH

Output width of one rendered scanline in hi-res (Modes 5/6, or pseudo-hires SETINI bit 3), in pixels — the DAC emits two output columns per pixel clock in this mode.

RENDER_DOT

The dot at which a visible scanline’s composited output becomes final for that line.

SCREEN_HEIGHT

Maximum visible height (overscan). Standard frames fill the first 224 rows.

SCREEN_WIDTH

Visible width of one rendered scanline in normal (non-hires) resolution, in pixels.