Module scheduler 

The master-clock lockstep scheduler — the run loop that owns the CPU + Bus.

Timing master: the 21.477 MHz SNES master crystal. The 65C816 drives the clock: each of its bus accesses advances the master clock by the region access speed (6/8/12), and that advance steps the PPU dot clock + SPC accumulator in lockstep (inside crate::Bus). This is LOCKSTEP, not catch-up — mid-instruction timing-master events (an HV-IRQ at a precise dot, a mid-scanline register write) land correctly without per-quirk patches (docs/adr/0001).

The scheduler’s job on top of the Bus is the frame structure: reset the CPU from the cart’s reset vector, step instructions until the PPU signals end-of-frame, and fire the per-line HDMA + the per-frame HDMA setup at the right scanline phases.

Structs

System

Owns the run loop. Determinism contract: same seed + ROM + input => bit-identical AV.