Module spc7110 

The SPC7110 board — Hudson’s decompression + memory-mapping ASIC (Far East of Eden Zero / Tengai Makyou Zero).

Clean-room port of ares’ SPC7110 component (ISC, sfc/coprocessor/spc7110/): a decompression unit (DCU, an adaptive binary range coder over 1/2/4bpp tile planes — decompressor), a data port unit (a seekable data-ROM cursor with auto-increment), an arithmetic-logic unit (16x16 multiply, 32/16 divide), and a memory-control unit (four independently-bankable 1 MiB data-ROM windows). There is no chip-ROM dump for the DCU/data-port/ALU — the algorithm runs entirely against the cart’s own PROM/DROM (docs/adr/0003).

SPC7110 owns its ROM/RAM mapping directly (like S-DD1/Super FX/SA-1): its $00-3F,$80-BF:8000- FFFF + $C0-FF:0000-FFFF window folds to a UNIFIED linear data-ROM address ((bank & 0x3F) << 16 | offset, ares mcuromRead’s doc comment) that a plain LoROM/HiROM board’s fold can’t express, and the register window additionally mirrors onto whole banks $50/$58.

Cartridge geometry: unlike every other coprocessor here, SPC7110 carts physically carry TWO ROM chips — a small plain “PROM” (CPU-executable program code, LoROM-style banks 00-0F) and a much larger “DROM” (compressed/plain data, addressed only through this board’s registers). A combined .sfc dump concatenates PROM then DROM. There is no header field or generic formula that recovers the split for every SPC7110 title (this project has exactly one SPC7110 ROM to validate against, mirroring the single-title validation basis already used for CX4/DSP-4/ST010/ OBC1): select uses Far East of Eden Zero’s known real physical chip sizes (1 MiB PROM + 4 MiB DROM, per ares’ own board database — see select’s own doc for the discrepancy this fixed against this project’s staged dump), else treats the whole image as DROM (the “no PROM” SPC7110 layout used by titles like Momotarou Dentetsu VII).

Bus window (bank:addr):

Region	Target
$00-3F,$80-BF:$4800-$483F, whole bank $50, whole bank $58	registers (DCU/data-port/ALU/memory-control)
$00-3F,$80-BF:$8000-FFFF, $C0-FF:$0000-FFFF	PROM (if present) or DROM, banked via $4830-$4833 + $4834. $40-$7D is genuinely UNMAPPED on this board (MappedAddr::Open) — ares’ real board database (board: SHVC-LDH3C-01, the exact board this title uses) maps the mcu ROM window only at these two ranges, NOT $40-$7D; an earlier session’s claim that boot code executes from $40-$7D was never checked against this database, and a watchpoint+disassembler trace found the opposite (code jumping there decodes as incoherent garbage)
$00-3F,$80-BF:$6000-$7FFF	battery SRAM (folds to banks 00-07), gated on $4830 bit 7

Structs

Spc7110Board

A cartridge carrying an SPC7110 (owns its ROM/RAM mapping directly — see the module doc).

Functions

select

Build a Spc7110Board for a cart detected as SPC7110 (board::select).