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Module sa1

rustysnes_cart::coproc

Module sa1 

Source
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The SA-1 board — the Super Accelerator system (a second 65C816 + ASIC) on the cartridge.

SA-1 (Nintendo’s “Super Accelerator 1”) is the most capable on-cart coprocessor: a second WDC 65C816 clocked at ~10.74 MHz (twice the S-CPU’s fast rate) plus a support ASIC. Unlike the DSP family there is no chip-ROM dump — the SA-1 program lives in the cartridge ROM, so the board is functional the moment an SA-1 cart loads (docs/cart.md, docs/adr/0003). Titles: Super Mario RPG, Kirby Super Star, Kirby’s Dream Land 3, Marvelous, SD F-1 Grand Prix, …

§Why this board is split across two crates

The one-directional chip-crate graph forbids rustysnes-cart from depending on rustysnes-cpu (docs/architecture.md). So this board owns the entire SA-1 system state — the $2200–$23FF register file, the Super-MMC ROM banking, BW-RAM (shared) + I-RAM (2 KiB internal), the arithmetic unit, the (normal + character-conversion) DMA, the variable-length bit unit, and the H/V timer — and exposes the SA-1 CPU’s memory view through the crate::board::Board second-CPU hooks. rustysnes-core (which already depends on rustysnes-cpu) instantiates the second rustysnes_cpu::Cpu, wires a thin bus adapter to these hooks, and steps it in the scheduler alongside the main CPU. See docs/scheduler.md §SA-1.

§Memory maps (clean-room from ares sfc/coprocessor/sa1, ISC)

S-CPU (main) view — handled by Board::read24/Board::write24:

Region (banks : addr)Target
$00-$3F,$80-$BF : $2200-$23FFSA-1 registers (S-CPU side)
$00-$3F,$80-$BF : $3000-$37FFI-RAM (2 KiB)
$00-$3F,$80-$BF : $6000-$7FFFBW-RAM (8 KiB block, selected by $2224)
$00-$3F,$80-$BF : $8000-$FFFFROM (Super-MMC blocks C/D)
$40-$4F : $0000-$FFFFBW-RAM (linear)
$C0-$FF : $0000-$FFFFROM (Super-MMC blocks via $C/D/E/Fxx)

SA-1 (second-CPU) view — handled by the second-CPU hooks: the same ROM/BW-RAM/I-RAM/regs plus the BW-RAM bitmap window ($60-$6F, 2/4 bpp) and the linear window ($40-$5F).

Structs§

Sa1Board
A cartridge carrying the SA-1 system: the S-CPU memory map plus the entire SA-1 ASIC + the SA-1 CPU’s memory view (the second 65C816 itself lives in rustysnes-core).

Functions§

select
Select an SA-1 board for rom, sizing BW-RAM from sram_size and the timer from region.