Expand description
The NEC µPD77C25 / µPD96050 LLE engine — the shared NEC DSP core.
One engine backs six SNES coprocessors (docs/cart.md §“the shared NEC core”): the
uPD7725 revision is the DSP-1/1A/1B + DSP-2/3/4 chip; the uPD96050 revision is the
ST010 / ST011. Each chip differs only in its firmware (program ROM + data ROM) and its
register widths, so this is a single firmware-parameterized core — implement it once, drive
each chip’s dumped program/data ROM through it.
This is a clean-room re-implementation of ares’ uPD96050 component (ISC) in safe
no_std Rust: the NEC DSP instruction word is a hardware fact, and the decode here mirrors
the published instruction encoding (OP / RT / JP / LD), not ares’ source layout. The host
interface (the DR data register, the SR status register, and the DP data-RAM port) is the
memory-mapped surface the SNES CPU sees.
§Host synchronization model
The real chip free-runs on its own ~7.6 MHz oscillator and hand-shakes the SNES CPU purely
through the RQM (“request for master”) status bit: the DSP raises RQM when it wants the
host to service the data register, the host’s access clears it, and the DSP spins on a
JRQM/JNRQM wait loop until serviced. Because RQM is the only observable coupling
between the two clocks (DSP-1 games always poll SR.rqm, never a wall-clock cycle count),
Upd77c25::run_until_rqm advances the engine to its next parked state after every host
data-register access. This keeps the bus boundary byte-exact and fully deterministic
(docs/adr/0004) without a free-running per-master-clock tick.
Structs§
- Upd77c25
- The NEC µPD77C25 / µPD96050 LLE engine.
Enums§
- Revision
- Which NEC DSP variant the firmware targets — selects the register widths.