Expand description
The Hitachi HG51B S169 core — the CX4 coprocessor’s CPU (Mega Man X2, Mega Man X3).
Clean-room port of ares’ HG51B component (ISC, component/processor/hg51b/). Unlike the
NEC DSP family (a fully separate chip program dumped to firmware), the HG51B’s PROGRAM lives
in the cartridge ROM the user already owns — it fetches 256-word pages into a 2-page on-chip
instruction cache from cart ROM through the same bus the S-CPU sees (cache()), architecturally
closer to this project’s GSU/SA-1 ports than to DSP-1. Only a small 3 KiB data ROM (a
trig/sqrt constant lookup table, cx4.rom) is a genuine external chip dump.
Fixed-width 16-bit instruction word; ~30 real mnemonics (ALU/shift/branch/load-store/RAM-ROM
access) decoded from the top nibble (see dispatch). A 3 KiB data RAM ($000-$BFF, folded
from a $000-$FFF address space per the real chip’s >=$C00 -> -$400 quirk) and a 1024-entry
24-bit data ROM back the math tables; 16 general-purpose 24-bit registers; an 8-deep hardware
call stack; a DMA unit and a suspend/wait state machine round out the chip.
Structs§
- Hg51b
- The HG51B S169 core (CX4’s CPU).
Traits§
- Hg51b
Bus - The host-facing memory surface the HG51B core reads/writes through.