Expand description
The Super FX board — the GSU wired into a LoROM cartridge.
Super FX carts (GSU-1: Star Fox, Stunt Race FX, Vortex; GSU-2: Yoshi’s Island, Doom) carry an
Argonaut GSU (crate::coproc::gsu::Gsu) plus dedicated Game Pak RAM that holds the plotted
bitmap. The board owns the ROM (shared, read-only) and the Game Pak RAM, intercepts the GSU
register window, and arbitrates the shared ROM/RAM bus between the SNES CPU and the GSU. There
is no chip-ROM dump — the GSU program lives in the cartridge ROM — so the board is
functional the moment a Super FX cart loads (docs/cart.md, docs/adr/0003).
§CPU-side memory map (LoROM Super FX, the de-facto board the cartridge DB encodes)
| Region (banks : addr) | Target |
|---|---|
$00-$3F,$80-$BF : $3000-$32FF | GSU registers + opcode cache window |
$00-$3F,$80-$BF : $8000-$FFFF | Game Pak ROM (LoROM windows) |
$40-$5F,$C0-$DF : $0000-$FFFF | Game Pak ROM (linear) |
$70-$71,$F0-$F1 : $0000-$FFFF | Game Pak RAM (the GSU plot bitmap) |
$00-$3F,$80-$BF : $6000-$7FFF | Game Pak RAM low window (8 KiB) |
§Bus arbitration (docs/cart.md edge case #3)
While the GSU runs with Go set it owns whichever of ROM/RAM its SCMR RON/RAN bits grant;
the CPU cannot read them. A CPU ROM read during GSU ROM ownership returns the hardware “snooze
vector” (ares CPUROM::read); a CPU RAM read during GSU RAM ownership returns open bus. With
true CPU/GSU interleaving (see below) the CPU genuinely can execute its own instructions
while a Go burst is in flight, so this arbitration is a live path, not just a narrow corner
case around the instant Go is set.
§Host-synchronization (Board::coprocessor_tick)
Setting Go (a CPU write to $301F, R15’s high byte) only arms the GSU — it does not run
it to completion inline, and does not even run one whole instruction inline. The Bus
(rustysnes-core) advances it by exactly one master clock per Board::coprocessor_tick
call, from inside its own per-master-tick loop (advance_master) — the same place the PPU
dot and the APU’s SMP-cycle release happen, called unconditionally every tick regardless of
whether a coprocessor is even present. This mirrors ares’s SuperFX : Thread cothread, which
the scheduler interleaves with the main CPU at native master-clock granularity
(sfc/coprocessor/superfx/superfx.cpp’s Thread::create + timing.cpp’s
Thread::synchronize after every access) — the CPU can do unrelated work, or even service a
second Go burst, in between two ticks of the first one, instead of only ever observing
the coprocessor’s result after an entire burst (or an entire multi-Go render split across a
left half and a right half) drains “atomically” inside the one bus write that armed it
(Gsu::tick doc has the detail on what is, and isn’t, deferred).
Structs§
- Super
FxBoard - A LoROM cartridge carrying a Super FX GSU + its Game Pak RAM.
Functions§
- select
- Select a Super FX board for
rom. The basemap_modeis informational (Super FX carts are LoROM-mapped); the GSU RAM is sized fromsram_size.