Expand description
The CX4 board — the Hitachi HG51B169 wired into a LoROM cartridge (Mega Man X2, Mega Man X3).
Clean-room port of ares’ HitachiDSP board wrapper (ISC, sfc/coprocessor/hitachidsp/),
Mapping == 0 only (the scheme both local games use — ares board SHVC-1DC0N-01). Unlike
DSP-1, the Hg51b program executes from the cart’s own ROM (see that module’s doc), so this
board is functional the instant the cart loads for CODE; only the 3 KiB data-ROM constant
table (cx4.rom) is a genuine external chip dump, and the chip stays inert (never silently
degraded, docs/adr/0003) until it’s supplied.
Bus window (bank:addr, $00-3F,$80-BF only):
| Region | Target |
|---|---|
$8000-FFFF | cart ROM (delegated to the wrapped base board) |
$6000-6BFF, $7000-7BFF | HG51B’s 3 KiB data RAM (Hg51b::read_dram) |
$6C00-6FFF, $7C00-7FFF | HG51B’s IO register block (Hg51b::read_io) |
$70-77:0000-7FFF | save RAM — falls through to the base board, whose own LoROM SRAM decode already covers this bank range (docs/cart.md’s LoROM SRAM table); no CX4-specific handling needed |
Execution trigger: writing the cache program-counter register ($7F4F) while the chip is
halted starts it, which then runs synchronously to its next halt (Hg51b::run_until_halt) —
the same run-to-completion host-sync pattern this project’s GSU/DSP-1 boards use.
Structs§
- Cx4Board
- A LoROM cartridge carrying a CX4 (Hitachi HG51B169).