Trait Hg51bBus 

pub trait Hg51bBus {
    // Required methods
    fn is_rom(&self, address: u32) -> bool;
    fn is_ram(&self, address: u32) -> bool;
    fn read(&mut self, address: u32) -> u8;
    fn write(&mut self, address: u32, data: u8);
}

The host-facing memory surface the HG51B core reads/writes through.

The S-CPU’s cart ROM (shared, read-only from the chip’s side) and any other externally-addressable region a specific board wires up (CX4 has none beyond ROM; read/write/is_rom/is_ram mirror ares’ HG51B::{read,write,isROM,isRAM} virtual hooks).

Required Methods

fn is_rom(&self, address: u32) -> bool

Whether address (a chip-relative linear address) is cart ROM.

fn is_ram(&self, address: u32) -> bool

Whether address is chip-visible RAM (CX4 has none; always false).

fn read(&mut self, address: u32) -> u8

Read a byte at a chip-relative linear address (cache refill, DMA, bus-port reads).

fn write(&mut self, address: u32, data: u8)

Write a byte at a chip-relative linear address (DMA only for CX4 — no chip-side RAM).

Implementors