Expand description
Instruction fetch / decode / execute for the 65C816, plus bus plumbing.
Behavior is modelled on the bsnes / ares wdc65816 reference cores (study-only; this is a
clean-room Rust implementation). The decimal-mode ADC/SBC digit-wise correction
follows bsnes algorithms.cpp exactly. Cycle counts use the standard 65C816 timing tables
with the variable adjustments documented in docs/cpu.md:
+1ifM = 0(16-bit memory / accumulator access),+1if the low byte ofDis non-zero (direct-page modes),+1on an indexed page-cross,+1branch taken,+1more on emulation-mode page-cross.