Module addr 

Addressing-mode resolution for the 65C816.

Each mode resolves to an effective 24-bit address (and, where relevant, whether an indexed access crossed a 256-byte page boundary — the documented +1 cycle penalty). Operand bytes are fetched from the program bank (PBR) by the executor’s instruction-fetch path.

Bank handling follows the hardware rules: direct-page and stack-relative effective addresses live in bank 0; (dp),Y / [dp] / abs,X etc. add the index/DBR and may carry into the next bank for the long forms. See docs/cpu.md (“Addressing modes”).

Structs

Effective

A resolved effective address plus the page-cross flag used for the indexed +1 penalty.

Enums

Mode

The enumerated 65C816 addressing modes the executor dispatches on.