Module mode 

The 7 real ARM processor modes.

A u8, not a Rust enum, because Regs::switch_mode deliberately mirrors the source’s own default:-falls-back-to-User/System behavior for any OTHER 5-bit pattern reachable via MSR — a real ARM CPU accepts an out-of-range mode field as “reserved/UNPREDICTABLE,” and this port’s fallback (treat it like User/System for banking purposes) matches Mesen2’s own choice rather than rejecting it outright.

Constants

ABORT

Entered on a memory abort.

BIT

Bit 4 is always set on every real mode value; ORed into switch_mode’s input unconditionally (matching the source), so a caller never needs to set it explicitly.

FIQ

Fast interrupt mode — the only mode with a fully private R8-R14 bank.

IRQ

Normal interrupt mode.

SUPERVISOR

Entered on SWI (software interrupt).

SYSTEM

Privileged mode that shares USER’s register bank (no SPSR of its own either).

UNDEFINED

Entered on an undefined-instruction trap.

USER

Unprivileged mode — the normal running state; no SPSR, no banked R13/R14 of its own (shares the same bank as SYSTEM).