pub enum Cop0Access {
Read {
src: u8,
dest: u8,
wide: bool,
},
Cop1(Cop1Access),
Tlb(TlbOp),
Eret,
Write {
dest: u8,
value: u64,
wide: bool,
},
}Expand description
A coprocessor access that EX resolved but must not itself perform.
Despite the name this now covers COP0, the TLB and COP1 control (Cop1).
They share a variant because they share the stage split below, not because
they are the same unit — the name is kept for churn reasons and this note
exists so it does not mislead as COP1 grows in Sprint 3.
The stage split is the manual’s, not a convenience: UM §4.6.9 describes the
CP0 bypass interlock as firing when “an instruction which caused an
exception reaches the WB stage and the subsequent instruction in the DC stage
requests a read of any CP0 register” — so a coprocessor read happens in
DC and a write happens in WB. Performing both in EX would make that
interlock unexpressible, which is the same mistake ADR 0007 exists to prevent
one level up.
Variants§
Read
Read COP0 register src into GPR dest, in DC.
Fields
Cop1(Cop1Access)
A COP1 control access, performed where the state lives.
Tlb(TlbOp)
A TLB instruction. Performed where the TLB lives, not in EX.
Eret
ERET — restore PC from EPC/ErrorEPC, clear EXL/ERL, clear
the link bit.
Cannot be resolved in EX like an ordinary redirect, because the target
comes out of COP0 rather than out of the instruction.
Write
Write value to COP0 register dest, in WB.
Trait Implementations§
Source§impl Clone for Cop0Access
impl Clone for Cop0Access
Source§fn clone(&self) -> Cop0Access
fn clone(&self) -> Cop0Access
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more