pub enum MemOp {
Load {
kind: LoadKind,
addr: u64,
dest: u8,
},
Store {
kind: StoreKind,
addr: u64,
value: u64,
},
LinkedLoad {
kind: LoadKind,
addr: u64,
dest: u8,
},
ConditionalStore {
kind: StoreKind,
addr: u64,
value: u64,
dest: u8,
},
Emux {
funct: u8,
code: u16,
ptr: u64,
len: u64,
dest: u8,
},
Cache {
addr: u64,
op: u8,
},
Fp {
op: Op,
addr: u64,
ft: u8,
},
Unaligned {
op: Op,
addr: u64,
rt: u64,
dest: u8,
},
}Expand description
A memory access EX computed and DC must perform.
EX resolves the effective address and hands the access to DC; it does not
touch the bus itself. That split is the point of the pipeline — DC is the
cycle the scheduler interleaves the RCP around (ADR 0007).
Variants§
Load
An aligned load into dest.
Fields
Store
An aligned store of value.
LinkedLoad
A load linked: an aligned load that also arms the link bit and
records the physical address in LLAddr (UM §16 p. 453).
Fields
ConditionalStore
A store conditional: stores value only if the link bit is set, and
writes the outcome (1 = stored, 0 = not) to dest either way.
Carrying dest is what makes this distinct from MemOp::Store — the
flag is architecturally visible even when nothing is written to memory
(UM §16 p. 487).
Fields
Emux
An EMUX emulator-extension operation (COP0 CO funct 0x20-0x3F).
Carried to DC because it needs the bus: xlog reads a string out of
guest memory and hands it to the host. execute is pure and cannot.
Fields
Cache
A CACHE maintenance operation.
Carries the effective address so DC translates it — the instruction can
raise a TLB fault — and the 5-bit operation selector so a trace can name
what was requested. No data moves.
Fields
Fp
An FP load or store (LWC1/LDC1/SWC1/SDC1).
Kept separate from MemOp::Load/MemOp::Store because the value
moves to or from the FP register file, and DC needs to know which —
a shared variant would need a “which file” flag anyway.
Unaligned
One half of an unaligned access. rt is needed for both directions: a
partial load merges into it, and a partial store merges out of it.