Function dispatch 

pub fn dispatch(
    cop0: &mut Cop0,
    exc: Exception,
    pc: u64,
    in_delay_slot: bool,
    bad_vaddr: u64,
) -> Dispatch

Perform the exception epilogue and return where to vector.

The order is the flowchart’s (UM Fig. 6-14, p. 201), and it matters:

1. Cause.ExcCode and Cause.CE.
2. BadVAddr — address errors and TLB exceptions only.
3. EntryHi / Context / XContext — TLB exceptions only (T-12-004).
4. If EXL was 0: Cause.BD and EPC. Otherwise both are left alone.
5. EXL ← 1.
6. PC ← vector.

pc is the faulting instruction’s address and in_delay_slot says whether it sits in a branch delay slot; when it does, EPC gets pc - 4 — the branch, not the delay-slot instruction — because that is where a handler must resume for the branch to be re-evaluated.

nmi is intercepted at the top: none of the six steps above describe it.