Function nmi 

pub fn nmi(cop0: &mut Cop0, pc: u64) -> Dispatch

Perform the exception epilogue and return where to vector.

The order is the flowchart’s (UM Fig. 6-14, p. 201), and it matters:

1. Cause.ExcCode and Cause.CE.
2. BadVAddr — address errors and TLB exceptions only.
3. EntryHi / Context / XContext — TLB exceptions only (T-12-004).
4. If EXL was 0: Cause.BD and EPC. Otherwise both are left alone.
5. EXL ← 1.
6. PC ← vector.

pc is the faulting instruction’s address and in_delay_slot says whether it sits in a branch delay slot; when it does, EPC gets pc - 4 — the branch, not the delay-slot instruction — because that is where a handler must resume for the branch to be re-evaluated. The NMI exception (UM §6.4.6, p. 185).

Kept out of dispatch because almost none of that function applies. NMI writes ErrorEPC, not EPC; it sets ERL, not EXL; and it writes no Cause at all — “the contents of all registers are preserved except for” ErrorEPC and four Status bits. Routing it through the general path would overwrite Cause.ExcCode with a code NMI does not have.

It is not maskable: “it occurs regardless of the settings of the EXL, ERL, and the IE bits in the Status register”. The one condition it does respect is the instruction boundary — unlike Cold and Soft Reset, “NMI is taken only at instruction boundaries”, and the caches and memory are preserved.

SR is what distinguishes it from a reset afterwards: the manual notes there is otherwise “no indication from the processor to differentiate between NMI & Soft Reset”.