Struct Dma 

pub struct Dma {
    pub channels: [Channel; 8],
    pub gp_enable: u8,
    pub hdma_enable: u8,
}

The 8-channel DMA controller plus the MDMAEN/HDMAEN enables.

Fields

channels: [Channel; 8]

The 8 channels.

gp_enable: u8

$420B MDMAEN — GP-DMA enable mask (write triggers the run).

hdma_enable: u8

$420C HDMAEN — HDMA enable mask.

Implementations

impl Dma

pub fn new() -> Self

Construct a power-on DMA controller (all channels open, no transfers pending).

pub fn write_reg(&mut self, ch: usize, reg: u8, val: u8)

Write a DMA channel register $43nA (or the $420B/$420C enables, handled by the bus). reg is the low byte ($00-$0A); ch is the channel index 0-7.

pub fn save_state(&self, w: &mut SaveWriter)

Write all 8 channels + the MDMAEN/HDMAEN enables into a "DMA0" section.

pub fn load_state( &mut self, r: &mut SaveReader<'_>, ) -> Result<(), SaveStateError>

The inverse of Self::save_state.

Errors

SaveStateError on truncated/corrupt input or a section with unconsumed trailing bytes.

pub const fn read_reg(&self, ch: usize, reg: u8) -> u8

Read a DMA channel register $43nA.

pub fn run_gp(&mut self, mask: u8, bus: &mut impl DmaBus) -> u32

Run all GP-DMA channels selected by mask ($420B write) to completion. The CPU is considered halted for the whole run; the returned value is the master-clock cost (the scheduler advances the clock by it). Ported from ares Channel::dmaRun.

pub fn service_hdma_line( &mut self, line: u16, vh: u16, bus: &mut impl DmaBus, ) -> u32

Service one scanline’s HDMA lifecycle: at V=0 reset the bookkeeping and load the tables, on each visible line (1..=vh) run one transfer, otherwise nothing. Returns the master-clock cost. Shared by the per-master-tick path (Bus::advance_master) and the in-GP-DMA interleave (Dma::run_gp via Self::service_hdma_during_gp) so HDMA stays scanline-accurate even while a GP-DMA is advancing the clock across line boundaries.

pub fn hdma_reset(&mut self)

Reset every channel’s HDMA bookkeeping at the start of a frame (V=0). ares hdmaReset.

pub fn hdma_setup(&mut self, bus: &mut impl DmaBus) -> u32

Per-frame HDMA setup: load each enabled channel’s table pointer + first line entry. Returns the master-clock cost. ares hdmaSetup + Channel::hdmaSetup/hdmaReload.

pub fn hdma_run(&mut self, bus: &mut impl DmaBus) -> u32

Run one visible-scanline’s HDMA for all active channels (ares hdmaRun → hdmaTransfer + hdmaAdvance). Returns the master-clock cost (the per-line budget).

Trait Implementations

impl Clone for Dma

fn clone(&self) -> Dma

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dma

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dma

fn default() -> Dma

Returns the “default value” for a type.