Struct Cpu

Source

pub struct Cpu {
    pub a: u8,
    pub x: u8,
    pub y: u8,
    pub pc: u16,
    pub sp: u8,
    pub status: StatusFlags,
    pub cycles: u64,
    pub stall: u8,
    pub jammed: bool,
    /* private fields */
}

Expand description

NES 6502 CPU

Cycle-accurate implementation of the MOS 6502 as used in the NES. All timing follows the NESdev Wiki specifications.

Fields§

§a: u8

Accumulator register

§x: u8

X index register

§y: u8

Y index register

§pc: u16

Program counter

§sp: u8

Stack pointer (points to $0100-$01FF)

§status: StatusFlags

Status flags

§cycles: u64

Total cycles executed

§stall: u8

Stall cycles (for DMA)

§jammed: bool

CPU jammed (halt opcodes)

Implementations§

Source §

impl Cpu

Source

pub fn new() -> Self

Create a new CPU in power-on state.

§Power-on State

A, X, Y: undefined (set to 0)
SP: $FD (after RESET pulls 3 bytes)
P: $34 (IRQ disabled)
PC: Read from RESET vector $FFFC-$FFFD

Source

pub fn reset(&mut self, bus: &mut impl Bus)

Reset the CPU.

Simulates the RESET interrupt sequence:

SP decremented by 3 (no writes)
I flag set
PC loaded from RESET vector ($FFFC-$FFFD)
Takes 7 cycles

Source

pub fn step(&mut self, bus: &mut impl Bus) -> u8

Execute one instruction and return cycles taken.

Handles interrupt polling and instruction execution. Returns the number of CPU cycles consumed.

Source

pub fn trigger_nmi(&mut self)

Trigger NMI (Non-Maskable Interrupt).

NMI is edge-triggered - call this when NMI line transitions from high to low.

Source

pub fn set_irq(&mut self, active: bool)

Set IRQ line state.

IRQ is level-triggered - will fire every instruction while line is low and I=0.

Source

pub fn irq_pending(&self) -> bool

Check if IRQ is pending.

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pub fn get_cycles(&self) -> u64

Get total cycles executed.

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pub fn is_jammed(&self) -> bool

Check if CPU is jammed (halted).

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pub fn get_state(&self) -> CpuState

Get current CPU state (for debugging/testing).

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pub fn tick(&mut self, bus: &mut impl CpuBus) -> bool

Execute exactly one CPU cycle with cycle-accurate bus synchronization.

This is the core of cycle-accurate emulation. Each call advances the CPU by exactly one cycle, calling on_cpu_cycle() before each memory access to keep PPU and APU perfectly synchronized.

Returns true when an instruction boundary is reached (ready for next instruction).

§Cycle-Accurate Timing

Each memory access calls on_cpu_cycle() BEFORE reading/writing, ensuring that PPU has advanced 3 dots and APU has advanced 1 cycle before the CPU observes the memory state. This is critical for accurate $2002 VBlank flag timing.

Source

pub fn read_cycle(&mut self, bus: &mut impl CpuBus, addr: u16) -> u8

Read a byte from memory with cycle callback.

Calls on_cpu_cycle() BEFORE the read, then performs the actual read. This is the cycle-accurate version of memory read.

§Arguments

bus - The cycle-aware bus implementing CpuBus
addr - 16-bit memory address to read from

§Returns

The 8-bit value at the specified address

§Timing

CPU Cycle:  |-------- read --------|
PPU Cycles: |--1--|--2--|--3--|
             ^ on_cpu_cycle() called here

Source

pub fn write_cycle(&mut self, bus: &mut impl CpuBus, addr: u16, value: u8)

Write a byte to memory with cycle callback.

Calls on_cpu_cycle() BEFORE the write, then performs the actual write. This is the cycle-accurate version of memory write.

§Arguments

bus - The cycle-aware bus implementing CpuBus
addr - 16-bit memory address to write to
value - 8-bit value to write

§Timing

CPU Cycle:  |------- write --------|
PPU Cycles: |--1--|--2--|--3--|
             ^ on_cpu_cycle() called here

Source

pub fn dummy_cycle(&mut self, bus: &mut impl CpuBus, addr: u16)

Perform a dummy read cycle (for timing purposes).

Some instructions require timing cycles where a read is performed but the value is discarded. This method handles those cases while still calling on_cpu_cycle() for proper PPU/APU synchronization.